1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device with buried bit lines and a method for fabricating the same.
2. Description of the Related Art
Most semiconductor devices include transistors. For example, in a memory device such as a DRAM, a memory cell includes a cell transistor such as a MOSFET. In general, in a MOSFET, source/drain regions are formed in a semiconductor substrate, and thus, a planar channel is formed between the source region and the drain region. Such a general MOSFET is referred to as a planar channel transistor.
As improvements in the degree of integration and the performance of a memory device are continuously demanded, a technology for fabricating a MOSFET faces physical limitations. For example, as the size of a memory cell shrinks, the size of a MOSFET shrinks, as a result of which the channel length of the MOSFET cannot help but be shortened. If the channel length of a MOSFET is shortened, data retaining properties are likely to deteriorate, whereby the characteristics of the memory device may be degraded.
In consideration of these problems, a vertical channel transistor (VCT) has been suggested in the art. The vertical channel transistor includes a pillar in which a vertical channel is formed. A source region and a drain region are formed in the upper and lower portions of the pillar. Any one of the source region and the drain region is connected with a bit line.
FIG. 1 is a view illustrating a conventional semiconductor device.
Referring to FIG. 1, a plurality of body lines 12 are formed on a semiconductor substrate 11 in such a way as to be separated from one another. Pillars 13 are vertically formed on the surfaces of the body lines 12. Buried bit lines 14 are buried in the body lines 12. The pillars 13 include first and second source/drain regions 16 and 18 and channel regions 17. Word lines 15 are formed on the sidewalls of the pillars 13 to extend in a direction crossing with the buried bit lines 14. Since the word lines 15 have vertical structures, vertical channels are formed.
In the conventional art shown in FIG. 1, the body lines 12 are formed by etching the semiconductor substrate 11 in consideration of the height of the pillars 13 including the channel regions 17. Thereafter, by etching the upper parts of the body lines 12, the pillars 13 are formed.
In the conventional art, in order to prevent punch-through P from occurring between adjacent buried bit lines 14, a predetermined height P1 should be secured under the buried bit lines 14. The height P1 for preventing the punch-through P should be approximately 80 to 90 nm including the depth of the first source/drain regions 16 lying under the buried bit lines 14. Therefore, because a total height H including the body lines 12 and the pillars 13 increases, high aspect ratio etching is required when forming the body lines 12.
As a result, in the conventional art, not only the high aspect ratio etching is required since the height of the pillars 13 should be considered when forming the body lines 12, but also aspect ratio further increases in order to prevent the punch-through P between the buried bit lines 14. As a consequence, pattern leaning may result.